CMOS Analog 집적회로 설계 전북대학교 방 준 호. 1. 기본 증폭 회로 해석 (1) The real world is analog ! Hearing Speaking Data Processing blocks Analog circuits Analog circuits.

Presentation on theme: "CMOS Analog 집적회로 설계 전북대학교 방 준 호. 1. 기본 증폭 회로 해석 (1) The real world is analog ! Hearing Speaking Data Processing blocks Analog circuits Analog circuits."— Presentation transcript:

1 CMOS Analog 집적회로 설계 전북대학교 방 준 호

2 1. 기본 증폭 회로 해석

3 (1) The real world is analog ! Hearing Speaking Data Processing blocks Analog circuits Analog circuits 1.Analog IC 및 MOS Technology Trends 1

4 (2) Analog IC designs will never go away because as end (natural) signal are analog, analog front ends are essential (amplifiers, filters, ADCs and DACs) radio transmission and reception is an analog task analog is faster than digital for some applications as speeds go up, digital signals must be treated as analog SOC (system on a chip) trends to make the analog designs more important than ever. 2 1.Analog IC 및 MOS Technology Trends

5 ANSI 의 표준화 규격의 ADSL 용 아날로그 Front-end 회로 (T1.413-2:DMT 방식 ) Analog Front-end 회 로구 조 및 특 성 수신 단 (Rx) Transconductor3.3V, － 1.2 ~ ＋ 1.2 Input linearity Low-pass Filter3rd-Elliptic, 1.1MHz, Gm-C High-pass Filter3rd-Butterworth, 138kHz, Gm-C Σ-Δ ADC (Modulator)12bit, 1MHz(50MHz), Cascade 2-2 AGC1(AGC2)0 ㏈ -31 ㏈, 5bit DAC control ADC Amplifier80dB, 315MHz, Folded Cacode(CMFB) ADC Comparator7-bit(1V@ 50 ㎒ ) 송신 단 (Tx) Line-driver(LD)98 dB, 15MHz, Fully-Differential Pre-driver(PD)-15 ㏈ -0 ㏈, 4bit DAC control, Low-pass Filter3rd-Elliptic, 138kHz, Gm-C Σ-Δ DAC (Demodulator) 12 bit at 1MHz/s, 50Msampling, 4th SSSB DAC Interpolator Filter 141tap, 24bit DC Bias Circuit 온도변화에 적응하는 전압 및 전류원 Non-overlaping Clock Generator3.3ns Non-overlaping time, 1.6ns delay 부가 회로 CMOS Switching CircuitON resistance 370[Ω] (3) Analog 집적회로 설계 과정 예 A. 시스템 Spec. 검토 3 1.Analog IC 및 MOS Technology Trends

6 B. 설계 사양에 따른 설계 방법과 구조결정 설계 사양을 만족하기 위한 필터함수 결정 필터의 감도 특성이 우수한 장점 설계 사양 능동필터 모의 방법 결정 Gyrator 직접모의법 함수 결정 Iksan National College Biquad 실현법 SFG (signal flow graph) 모의법  VV o i 4 1.Analog IC 및 MOS Technology Trends

7 C. 회로 설계 Passive Filter 설계 Active Filter 설계 5 1.Analog IC 및 MOS Technology Trends

8 D. 시뮬레이션 (HSPICE) 6 1.Analog IC 및 MOS Technology Trends

9 E. Layout 및 Chip 제작 (1) Layout(2) Fabrication 7 1.Analog IC 및 MOS Technology Trends

10 F. Chip Test (1) Pin block (2) Test 8 1.Analog IC 및 MOS Technology Trends

11 2. MOS Transistor 의 기초 nMOS n+ Poly-Si SiO 2 P-sub pMOS p+ Poly-Si SiO 2 n-well p-sub n+ W L p+ W L gate(G) source(S)drain(D) bulk(B) gate(G) source(S)drain(D) bulk(B) (1) MOS Transistor 의 물리적 구조 2. MOS Transistor 의 기초 9

12 (2) MOS Transistor 의 Basic Operations (nMOS) Cutoff n+ P-sub +++++ S G D B V GS < V TH V GD < V TH I DS = 0 V GS > V TH V GD > V TH V DS < V GS - V TH. I DS = b [(V GS -V TH ) V DS - V DS 2 ] 1212 b = m C ox = m W L e o e ox t ox W L V GS > V TH V GD < V TH V DS > V GS - V TH. I DS = (V GS - V TH ) 2 b2b2 Linear(triode) n+ P-sub S G D B channel depletion region Saturation n+ P-sub S G D B 2. MOS Transistor 의 기초 10

13 (3) Body Effect n+ P-sub S G D B n+ P-sub S G D B depletion region IV BS1 I < IV BS2 I V TH = V TH0 +  ( I  s I - V BS - I  s I ) V TH0 = V TH ( when V BS = 0 )  : body effect parameter = 2  si qN A / C ox 11 2. MOS Transistor 의 기초

14 (4) Channel-Length Modulation Effect n+ P-sub S G D B n+ P-sub S G D B depletion region IV DS1 I < IV DS2 I : channel-length modulation parameter xdxd I DS =  n C ox (V GS - V TH ) 2 1212 W L eff =  n C ox (V GS - V TH ) 2 1212 W L-x d =  n C ox (V GS - V TH ) 2 (1 + V DS ) 1212 WLWL 1 L =  x d V DS 12 2. MOS Transistor 의 기초

15 (5) MOSFET I-V Curves IDSIDS linearsaturation = 0 V DS 0 (I DS ) 1/2 cutoffon(saturation) V GS 0 V TH IDSIDS linear saturation V DS 0 V GS (I DS ) 1/2 V GS 0 V TH0 V TH (V BS ) IV BS I I DS - V DS I DS - V GS 13 2. MOS Transistor 의 기초

16 (6) MOSFET Drain-source Current Summary G D S B G D S B nMOSFET (V THn > 0) I DS pMOSFET (V THp < 0) I DS = 0 I DS = b n [ (V GS -V THn )V DS - V DS 2 ] 1212 bn2bn2 I DS = (V GS - V THn ) 2 (1 + n V DS ) Cutoff Linear Saturation I SD = 0 I SD = b p [ (V SG -V THp )V SD - V SD 2 ] 1212 bp2bp2 I SD = (V SG - V THp ) 2 (1 + p V SD ) Cutoff Linear Saturation 14 2. MOS Transistor 의 기초

17 V DD =+5V R B =10k  VRVR V SS =-2V V BB =-5V V TH = V TH0 +  ( I  s I - V BS - I  s I ) V TH0 = 0.8 V  = 0.41 V I  s I = 0.7 V V BS = - 3 V = 1.25 V  n C ox = 53.3  A/V 2 W/L = 20  m /2.0  m  1 =  n C ox (W/L) = 533  A/V 2 M 1 in saturation M1M1 I RB = I M1 V DD -V R RBRB =  1 (V GS1 - V TH1 ) 2 1212 =  1 (V R - V SS - V TH1 ) 2 1212 V R = + 0.54 V or -2.42 V I RB = I M1 = 445.68  A 15 실습 문제 2-1 : Bias point 계산 2. MOS Transistor 의 기초

18 V DD =+5V V OUTQ V DD = 0V V TH0 = 0.8 V  = 0.41 V I  s I = 0.7 V  n C ox = 20  A/V 2 (W/L) 1 = 30  m /2.0  m 실습 문제 2-2 : Bias Level Shifter 의 Bias point 계산 V INQ =? M2M2 R 1 =30k  R 2 =20k  M1M1 (W/L) 2 = 20  m /2.0  m Bias Level Shifter 회로의 출력전압 (V OUTQ ) 을 2.5V 로 얻어내기 위하여 V INQ 에 몇 V 를 인가하여야 하는가 ? ( 단. 모든 MOS 는 Saturation 에서 동작하며 Channel length 효과는 무시함.) 16 2. MOS Transistor 의 기초

19 (1) Nonlinear operations 3. Small-Signal Analysis V IN f() V OUT = f (V IN ) : Nonlinear function ( 비선형 함수 ) V IN V OUT V IN 0 0 0t t V OUT Nonlinear transfer curve transfer curve 계산이 복잡 Linear 모델 필요 3.Small-Signal Analysis 17

20 (2) Linearization of Nonlinear operations V IN =V INQ + V in V OUT V IN 0 0 0t t V OUT = V OUTQ + V out bias (Q) transfer curve 입력과 출력 신호들은 두개의 성분, bias(Q) 와 small-signal 신호를 가진다. V INQ 0 t V in 0 t V INQ V in A V * V in = V out V OUTQ A V = dV out /dV in I Q small-signal V OUT = V OUTQ + V out V IN = V INQ + V in V OUTQ + A Vi * V in f() small-signal model linear operations, small-signal parameters depend on bias point 그래프의 기울기 = 전압의 증폭도 18 3.Small-Signal Analysis

21 (3) MOSFET 의 Small-signal model (Low-frequency) V GS = V GSQ +  V GS I DS = I DSQ +  I DS = I DS (V GS, V DS, V BS,) V DS = V DSQ +  V DS V BS = V BSQ +  V BS I DS =  I DS  V GS Q  V GS  I DS  V DS Q  V DS  I DS  V BS Q  V BS ++ I DS =  V GS  V DS  V BS ++ gmgm gogo g mb gmgm = transconductance =  I DS  V GS Q  I DS  V DS Q  I DS  V BS Q = gmgm =  (V GSQ - V TH ) (1 + V DSQ ) = 2  I DSQ (1 + V DSQ ) = 2  I DSQ = gogo = output conductance g mb = back-gate transconductance =  (V GSQ - V TH ) 2 = = I DSQ = gOgO g mb 1212  I DSQ  1 + I DSQ 1 r o  I DS  V TH  V BS Q = = gmgm     I  I-V BSQ = gmgm gmgm >> g mb >> g o 19 3.Small-Signal Analysis

22 (4) Small-signal 등가회로 (1) 20 v I = V GS + v gs v O = V O + v o (1) 소신호 성분 무시 할 때 I O =  n C ox (V GS - V TH ) 2 1212 W L V DD - V O R L ( if  0 ) I O =  n C ox (V GS - V TH ) 2 R L 1212 W L V O = V DD - (2) 소신호 성분 포함 할 때 i O =  n C ox (V GS + v gs - V TH ) 2 1212 W L V DD - (V O + v o ) R L ( if  0 ) i O =  n C ox { (V GS - V TH ) v gs + } W L v o = - R L V DD RLRL v O = V O + v o M V GS ioio v i = v gs vIvI v gs 2 2 에 의한 왜곡율 10% 이내 조건 v gs 2 3.Small-Signal Analysis

23 21  n C ox { (V GS - V TH ) v gs } W L v o = - R L I v gs I < 0.2 (V GS - V TH ) 조건을 만족한다면  n C ox (V GS - V TH ) v gs W L i o = v o = - R L i o 이므로 gmgm V DD RLRL vovo M ioio vivi V B 전압 = 0 일때 (4) Small-signal 등가회로 (2) 3.Small-Signal Analysis roro Body effect 무시한 등가회로 T 형 등가회로 RLRL v in v gs + - G g m v gs D BS v out roro RLRL v in v gs + - G g m v gs g mb v bs D BS v out r o =1/g o G D B S isis rsrs isis

24 (5) Small-signal model 활용 예제 V TH = V TH0 +  ( I  s I - V BS - I  s I ) V TH0 = 0.8 V  = 0.41V I  s I = 0.7 V V BS = 0 V = 0.8 V  n C ox = 53.3  A/V 2 W/L = 20  m /2.0  m  1 =  n C ox (W/L) = 533  A/V 2 V DD =+5V R L =100k  V OUT V IN V SS =-5V M1M1 = 0.05 V -1 Input Signal V IN = -4 + 0.01 sin(  t) bias V INQ + small signal V IN Direct(Nonlinear) Method V DD -V OUT RLRL = (V GS1 -V TH1 ) 2 (1+ V DS ) 1212 = (V IN -V SS -V TH1 ) 2 [1+ (V out -V SS )] 1212 (V IN -V SS -V TH1 ) 2 (1+ V SS ) - V DD /R L (V IN -V SS -V TH1 ) 2 + 1/R L  1 /2 V OUT == 19.99[0.01sin(  t) + 0.2] 2 -5 = ? 1.33[0.01sin(  t) + 0.2] 2 +1 Small-Signal (Linear) Analysis RLRL v in v gs1 + - G g m1 v gs1 g mb1 v bs1 D BS v out r o1 =1/g o1 Bias I Q = (V GSQ -V TH1 ) 2 = 10.7  A V OUTQ = V DD -I Q R L = 3.93V 1212 = 2   I Q gmgm = 106.8  A = I Q gogo = 0.54  A by KCLg m1 v gs1 + g mb1 v bs + g o1 v out + v out /R L 0 = g m1 v gs1 + g o1 v out + v out /R L = v out v in A V = g m1 g o1 +1/R L = - = - 10.13 v out = A V. v in = -0.1013 sin (  t) V OUT = V OUTQ + v out = 3.93 -0.1013 sin (  t) 22 3.Small-Signal Analysis

25 (1) Basic MOS Amplifiers 4. Basic MOS Amplifiers & Small-Signal Analysis V DD RLRL v out v in V SS D G S V DD RLRL v out V GG V SS D G S v in V DD RLRL v out VBBVBB D G S v in V SS CS(Common-Source Amp.) CG(Common-Gate Amp.) CD(Common-Drain Amp.) 구조구조 Input Output gate - source drain - source drain - gate gate - drain source - gate source - drain 23 4. Basic MOS Amplifiers & Small-Signal Analysis

26 V DD RLRL v out v in V SS D G S (2-1) 저항부하를 갖는 CS Amplifier 전압 이득 (Voltage Gain) : v out v in A V = RLRL v in v gs + - G g m v gs g mb v bs D BS v out r o =1/g o By KCL @ v out - node g m v gs + g mb v bs + g o v out + v out /R L 0 = g m v gs + g o v out + v out /R L = v out v in gmgm g o +1/R L = - A V = gmgm 1/r o +1/R L = - = - g m (r o II R L ) = - g m r o = 2m C ox W/L IDID - 24 (2) CS Amplifiers 의 Small-Signal Analysis 4. Basic MOS Amplifiers & Small-Signal Analysis

27 (2-2) Ideal DC 전류원 부하를 갖는 CS Amplifier 전압 이득 (Voltage Gain) : v out v in A V = By KCL @ v out - node g m v gs + g mb v bs + g o v out 0 = g m v gs + g o v out = v out v in gmgm gogo = - A V = gmgm 1/r o = - = - g m r o = 2m C ox W/L IDID - 25 V DD M v out v in IDID v gs + - G g m v gs g mb v bs D BS v out r o =1/g o 는 L 에 반비례 하므로 AVAV WL IDID 4. Basic MOS Amplifiers & Small-Signal Analysis 전압이득이 Bias 전류 ID 에 영향 받음

28 (2-3) MOS 다이오드를 부하로 사용하는 CS Amplifier 전압 이득 (Voltage Gain) : v out v in A V = g m1 g m2 + g mb2 + 1/r o1 + 1/r o2 g m2 v gs2 g mb2 v bs2 v out r o2 =1/g o2 g m1 v i r o1 vivi + - = - ~ g m1 A V = ~ g m2 - (W/L)1 (W/L)2 Load impedance 낮음  RC 시상수 작음  주파수 특성 우수  광대역 증폭기에 적합 = - V DD M1 v out v in M2 ioio 26 전압이득이 Bias 전류 ID 와 무관하고 W/L 에 의해 결정됨 4. Basic MOS Amplifiers & Small-Signal Analysis

29 (2-4) 전류미러 (Current mirror) 를 부하로 사용하는 CS Amplifier v out v in A V = g m1 (r o1 ll r o2 ) = - ~ V DD M1 v out M2 ioio M3 vivi g m1 v i v out r o2 vivi + - r o1 (2-5) CMOS inverter 형 CS Amplifier V DD M1 v out M2 vivi g m1 v i v out vivi + - r o1 g m2 v i r o2 v out v in A V = ( g m1 + g m2 ) ( r o1 ll r o2 ) = - ~ 27 4. Basic MOS Amplifiers & Small-Signal Analysis 소신호 등가회로 DC Bias 전류 = 0

30 (2-6) CS Amplifier 의 주파수 특성 (High frequency) v out (s) v in (s) A V (s) = g m r o (1+ s/  p1 ) V DD M1 v out v in = IDID RsRs v out g m1 v i roro vivi + - CICI v out g m1 v i r o1 vivi + - CICI C GD CLCL (1+g m r o ) C GD (1+ g m r o ) 1 C I = (C GS +C GB ) Miller 정리 (1+ s/  p2 ) 1 R s [ C 1 + C GD (1+g m r o ) ] =  p1 1 r o [ C L + C GD (1+ g m r o ) ] =  p2 1 Dominant pole ( 우수극점 )  주파수 특성에 영향 Nondominant pole ( 비우수극점 ) 28 4. Basic MOS Amplifiers & Small-Signal Analysis C AB AB

31 (3-1) 이상적인 전류원 부하를 갖는 CG Amplifier V DD I DC v out V GG D G S v in ioio 전압 이득 (Voltage Gain) : v i rsrs i s = g m1 v i = - v out v in A V = = - v o = ( g m1 r o + 1 ) v i = - i s r o + v i ( g m1 r o + 1 ) 전압이득  1 보다 조금 (+) 값 29 (3) CG Amplifiers 의 Small-Signal Analysis 4. Basic MOS Amplifiers & Small-Signal Analysis v in g m v gs g mb v bs v out r o =1/g o T 형 등가회로 + - v out isis vivi isis rsrs roro isis

32 (3-2) 저항 부하를 갖는 CG Amplifier 입력 저항 (Input Resistance) : vxvx ixix R in = By KCL @ v x - node I x + g m v gs + g mb v bs + g o (v out -v x ) 0 = = vxvx ixix g m + g mb + g o R in = gmgm V DD RLRL v out V GG V BB D G S v in I x + g m (0-v x ) + g mb (0-v x ) + g o (v out -v x ) By KCL @ v out - node g m v gs + g mb v bs + g o (v out -v x ) + v out /R L 0 = g m (-v x ) + g mb (-v x ) + g o (v out -v x ) + v out /R L = = = 1 + g o R L RLRL v gs + - G g m v gs g mb v bs D B S v out r o =1/g o vxvx - + ixix 출력 저항 R L 이 0 일 때  입력저항 R in  출력 저항 R L 이 oo 일 때  입력저항 Rin   전류원 입력을 받고 전류를 출력하기에 적합 30 4. Basic MOS Amplifiers & Small-Signal Analysis

33 (3-3) CG Amplifier 의 주파수 특성 V DD v out D G S v in RsRs RLRL RLRL G g m v gs g mb v bs D C1C1 S v out roro vivi C2C2 C I = (C GS +C BS ) 1 ( R s II R i ) C 1 =  p1 C 2 = (C GD +C BD ) 1 R s C 1 g m + g mb 1 RsRs 1 C1C1 1 R s C 1 RsRs 1 WLC ox = + W CGSO+ L CBS 2 3 우성극점의 크기가 CS Amplifier 에 비하여 크다  CG Amplifier 가 CS Amplifier 보다 주파수 특성 우수 31 4. Basic MOS Amplifiers & Small-Signal Analysis

34 (4-1) 이상적인 전류원 부하를 갖는 CD Amplifier v in + - G g m v gs g mb v bs D S roro V DD v out D G S v in I DC v out 전압 이득 (Voltage Gain) : v gs = v i - v o v out v in A V = = ( g m + g mb + 1 ) 전압이득  g mb 는 g m 의 10 내지 30% 이므로 전압 이득은 1 보다 조금 작은 양 (+) 의 수이다. v bs = - v o By KCL at node S roro gmgm = gmgm g m + g mb 1 32 (4) CD Amplifiers 의 Small-Signal Analysis 4. Basic MOS Amplifiers & Small-Signal Analysis

35 (4-2) 저항 부하를 가진 CD Amplifier 출력 저항 (Output Resistance) : vyvy iyiy R out = v y /R L + g o v y = i y + g m v gs + g mb v bs = vyvy iyiy g m + g mb + g o + 1/R L R in = g m + 1/R L RLRL v in v gs + - G g m v gs g mb v bs D B S r o =1/g o vyvy - + iyiy i y + g m (0-v y ) + g mb (0-v y ) By KCL @ v out - node = = 1 1 V DD RLRL v out VBBVBB D G S v in V SS V in 0 = gmgm 1 II R L = gmgm 1 전압 이득 (Voltage Gain) : v out v in A V = = ( g m + g mb + 1 ) r o II R L gmgm 33 4. Basic MOS Amplifiers & Small-Signal Analysis a b b a

36 RLRL g m v gs g mb v bs roro V DD RLRL v out VBBVBB D G S v in V SS 34 (4-3) CD Amplifier 의 주파수 특성 (High Frequency) vsvs CLCL RSRS C GB C GD C GS vsvs  -3dB(input) RsRs 1 = + C GB + C GS CD Amplifier 의 주파수 특성  CG Amplifier 과 CS Amplifier 보다 우수 g mb g m + g mb C GD = CLCL g m + g mb ~ 4. Basic MOS Amplifiers & Small-Signal Analysis

37 V DD RLRL v out v in V GG V BB RSRS RoRo 35 실습 문제 4-1 : CG Rs 삽입시 출력측에서 본 저항 (Ro) 구하기

38 4. Basic MOS Amplifiers & Small-Signal Analysis v gs + - G g m v gs g mb v bs D S v out roro vxvx + ixix - VSVS V DD RLRL v out v in V GG V BB RSRS RoRo RSRS 36 실습 문제 4-1 풀이 : CG Rs 삽입시 출력측에서 본 저항 (Ro) 구하기

39 g m2 v gs2 + g mb2 v bs2 + g o2 (v out -v a ) = v out g o1 (1+ g o2 R L ) A v = g m1 [ R L II{g m2 (r o2 II R L ) r o1 }] g m2 (-v a ) + g mb2 (-v a ) + g o2 (v out -v a ) By KCL @ v out - node = = 1+ V DD RLRL v out v in V SS v GG M1M1 M2M2 CG CS RLRL v gs2 + - G2 g m2 v gs2 g mb2 v bs2 D2 B1, B2S1 v out r o2 =1/g o2 v gs1 + - g m1 v gs1 g mb1 v bs1 r o1 =1/g o1 v in vava S2D1G1 v out RLRL = - By KCL @ v a - node g m1 v gs1 + g mb1 v bs1 + g o1 v a v out RLRL = - = g m1 v in + g o1 v a v in g m1 R L g m2 + g mb2 + g o2 - - 37 (5) Cascode Amplifiers 의 Small-Signal Analysis 4. Basic MOS Amplifiers & Small-Signal Analysis r o1 RoRo r o2 CG 출력저항

40 (6-1) Differential signal 와 Single ended signal (1) 38 (6) Differential Amplifiers 의 Small-Signal Analysis v out v in + - + - Single ended signal v out v in + - + - Differential signal v in + - CM level t tt 4. Basic MOS Amplifiers & Small-Signal Analysis

41 Differential signal advantage 39 V DD RLRL v o1 v i1 M1M1 M2M2 v o2 RLRL v i2 CM level v in1 v in2 v out1 v out2 High rejection of environmental noise Change in input CM level : change is bias I, Gm or clipping ! Differential signal disadvantage Sensitive to input common mode level CM level v in1 v in2 v out1 v out2 t t (6-1) Differential signal 와 Single ended signal (2) 4. Basic MOS Amplifiers & Small-Signal Analysis

42 40 4. Basic MOS Amplifiers & Small-Signal Analysis V DD RDRD M1M1 M2M2 RDRD V SS I D1 I D2 V DD RDRD v o1 v i1 M1M1 M2M2 v o2 RDRD v i2 (6-2) Tail current I SS I D1 I D2 출력 공통모드 전압 (V oCM ) 이 입력 공통모드 전압 (V iCM ) 에 영향을 받는다. Tail current 첨가 v o1 v i1 v o2 v i2

43 g m1 (v i1 - v c ) = 0 A v = g m1 R L By KCL @ v o1 - node = = v o1 - v c r o1 + By KCL @ v 02 - node - - V DD RLRL v o1 VBVB V SS v i1 M1M1 M3M3 M2M2 v o2 RLRL v i2 I ss I1I1 I2I2 vcvc RLRL D2 S2 + - g m2 v gs2 v gs2 v 02 G2 RLRL D1 S1 v gs1 r o1 + - g m1 v gs1 v o1 G1 r o2 VCVC r o3 v i1 v i2 Differential Signals v i1 - v i2 = = vivi v o1 - v o2 = - R L (I 1 - I 2 ) = - R L  I = vovo Current Equation I 1 =  (v i1 - v c - V TH ) 2 I 2 =  (v i2 - v c - V TH ) 2 I 1 + I 2 = I SS  I = I 1 - I 2 =   v i -  v i 2 2I SS  = vovo vivi Q:  v i =0 AvAv Voltage Gain II vivi Q:  v i =0 -R L = - R L G M GMGM = Q:  v i =0 II vivi  I SS  I 1Q == g m1(2) =  A v = - g m1 R L v o1 RLRL + g m2 (v i2 - v c ) = 0 v o2 - v c r o2 + v o2 RLRL + v i1 - v i2 v o1 - v o2 g m1 (r o II R L ) Assume M1 and M2 are identical for r o >> R L (6-3) 저항성 부하를 갖는 NMOS 차동증폭기 (1) Small signal analysis 41

44 42 Half-circuit 개념을 이용한 Small signal analysis RLRL M1M1 D1 S1 v gs1 r o1 + - g m1 v gs1 G1 RLRL RLRL M1M1 ½ M3½ M3 Differential mode Half circuit Common mode Half circuit D1 S1 v gs1 r o1 + - g m1 v gs1 G1 RLRL 2r o3 V DD RLRL V o1 V in1 M1M1 M2M2 V o2 RLRL V in2 V SS I D1 I D2 M3M3 DC Bias (6-3) 저항성 부하를 갖는 NMOS 차동증폭기 (2) 4. Basic MOS Amplifiers & Small-Signal Analysis

45 43 Active input common mode range V DD RDRD V out1 V in, CM M1M1 M2M2 RDRD VbVb M3M3 V out2 V1V1 V2V2 V in,CM V TH Small-signal differential mode voltage gain 4. Basic MOS Amplifiers & Small-Signal Analysis        TH SS DDDCMinTHGS V I RVVVVV 2 min)(,331 (6-3) 저항성 부하를 갖는 NMOS 차동증폭기 (3)

46 44 (6-4) 능동 (Active) 부하를 갖는 NMOS 차동증폭기 (1) V DD V i1 M1M1 VoVo V i2 V SS M4M4 M5M5 DC bias M2M2 Common mode input  상쇄되어 없어짐 Differential mode input  두배 Differential to single ended amplifier V DD V i1 M1M1 VoVo V i2 V SS M4M4 M5M5 DC bias M2M2 M3M3 M3M3 Current mirror 4. Basic MOS Amplifiers & Small-Signal Analysis

47 45 출력저항 ( R O ) (6-4) 능동 (Active) 부하를 갖는 NMOS 차동증폭기 (2) 4. Basic MOS Amplifiers & Small-Signal Analysis CG 출력저항 CG 입력저항 Current mirror

48 46 차동모드 트랜스컨덕턴스 (G md ) (6-4) 능동 (Active) 부하를 갖는 NMOS 차동증폭기 (3) 4. Basic MOS Amplifiers & Small-Signal Analysis

49 47 * 유도과정 : 참고 ( 박홍준 ; CMOS 아날로그 집적회로 p337) 공통모드 트랜스컨덕턴스 (G mc ) (6-4) 능동 (Active) 부하를 갖는 NMOS 차동증폭기 (4) 4. Basic MOS Amplifiers & Small-Signal Analysis

50 48 공통모드 이득 제거율 ( Common mode rejection ratio : CMRR ) (6-4) 능동 (Active) 부하를 갖는 NMOS 차동증폭기 (4) 4. Basic MOS Amplifiers & Small-Signal Analysis CMRR = A vd A vc - + V in_com V out V SS V DD 공통모드 신호 증폭

51 49 Active input common mode voltage range (CMR) CMR : 최대의 이득을 얻기 위해 모든 트랜지스터 들이 saturation 영역에서 동작하기 위한 입력 전압범위 CMR min CMR max V DD V i1 M1M1 VoVo V i2 V SS M4M4 M5M5 DC bias M2M2 M3M3 NMOS 차동입력단 (6-4) 능동 (Active) 부하를 갖는 NMOS 차동증폭기 (5) 4. Basic MOS Amplifiers & Small-Signal Analysis

52 50 Active input common mode voltage range (CMR) V in - M1M1 M2M2 V DD M5M5 M3M3 V SS M4M4 V in + CMR min CMR max PMOS 차동입력단 NMOS 차동입력단 VSSVDD (6-4) 능동 (Active) 부하를 갖는 NMOS 차동증폭기 (6) 4. Basic MOS Amplifiers & Small-Signal Analysis

53 (6-5) CS Push-Pull Amplifier g m2 v sg2 = g m1 v gs1 + v out /r o1 + v out /r o2 v out  A v = M1 과 M2 는 각각 Amplifier 이면서 Load 로 동작됨 = By KCL @ v out - node v in - V DD v out v in V SS M1M1 M2M2 V DD v out v in V SS M1M1 M2M2 V B2 + - + - V B1 v sg2 + - S2 g m2 v sg2 S1 v out r o2 v gs1 + - g m1 v gs1 r o1 v in D2 G1 G2 v in D1 M1 과 M2 의 Gate 에 Bias Circuit 가 요구됨 g m2 (0-v in ) = g m1 (v in -0) + v out /r o1 + v out /r o2 (g m1 + g m2 ) (r o1 II r o2 ) 51 4. Basic MOS Amplifiers & Small-Signal Analysis

54 52 (1) Passive & Active Loads 5. Current Sources & Mirrors Passive Load Ideal Current Source Active Load 구조구조 Loading Biasing IBIB r op  I MP (V DD - V OUTQ )/ R L RLRL V DD RLRL v out v in V SS Passive Load V DD v out v in V SS Ideal Current Source IBIB V DD v out v in V SS Active Load V GG 5. Current Sources & Mirrors

55 (2) Ideal & Active Current Sources Equivalent Circuit I-V Curve Ideal Current Source Output current ( I out ) should be independendent of an output voltage ( V out ) Active Current Source Characteristics V out + - I out V out + - I out V out I out V out Operating range Slope = dI out dV out = R out -1 Operating Range Large Signal Analysis Operating Resistance R out Small Signal Analysis 53 5. Current Sources & Mirrors

56 (3) Simple NMOS Current Sources Equivalent Circuit I-V Curve Output Resistance V out + - I out I out = I DS V out = V DS Slope = dI out dV out = r out -1 VBVB vxvx v gs + - g m v gs roro + - ixix V DS(sat) =V GS -V TH =V B -V TH I DS(sat) =  V GS - V THn ) 2 =  2 2I DS(sat)   V out  = vxvx  R out = ixix = r o 1 gogo = 54 5. Current Sources & Mirrors

57 (4) Cascode Current Sources Equivalent Circuit Characteristics vxvx  R out = ixix = r o1 + r o2 + (g m2 r o2 )r o1  (g m2 r o2 )r o1 Output Resistance V out + - I out V B1 V B2 M2M2 M1M1 + - vxvx ixix vxvx v gs2 + - g m2 v gs2 r o2 + - ixix v gs1 + - g m1 v gs1 r o1 Operating Range Down to 2  More Stacking : Problem for Low-Supply Applications 55 5. Current Sources & Mirrors

58 (5) Advanced Cascode Current Sources Equivalent Circuit Characteristics vxvx  R out = ixix = r o1 + r o2 + (A+1)(g m2 r o2 )r o1  A(g m2 r o2 )r o1 Output Resistance A V B1 V B2 M2M2 M1M1 + - vxvx ixix + - g m2 v gs2 + g mb2 v bs2 + g o2 (v x -v y ) g m2 [A(0-v y )-v y ]+ g o2 (v x -v y ) = By KCL @ v x -node ixix vxvx v gs2 + - g m2 v gs2 r o2 + - ixix v gs1 + - g m1 v gs1 r o1 + - vyvy = g m1 v gs1 + g o1 v y = By KCL @ v y -node ixix g o1 v y = 56 5. Current Sources & Mirrors A (0-v y )A

59 (6) Basic Current Mirror M2M2 I out V SS IinIin M1M1  M 1 : Current Input M 2 : Current Output M 1 와 M 2 가 Ideal Matching 일때, I 1 = I 2 Operating Range : Down to  Output Resistance : R out = r o2 Mismatch Problem I out I in = ( ) 2 ( V GS -V TH2 ) 2 ( 1+ V DS2 ) W L 1212 m C ox ( ) 1 ( V GS -V TH1 ) 2 ( 1+ V DS1 ) W L 1212 m C ox  transistor size W/L  threshold voltage  V DS 57 5. Current Sources & Mirrors

60 (7) Wilson Current Mirror (1) M1, M2 는 소신호 피이드백 경로가 됨 V 2 가 증가하여 전류 I out 이 증가하면 V 1 증가하므로 M1 의 증폭으로 V 2 가 크게 감소함 결국 V GS3 가 감소 하게 되어 I out 이 감소하게 됨. 이와 같은 과정은 역으로도 진행되어 I out 이 일정하게 유지됨 --> 소신호 출력저항이 큰값 58 5. Current Sources & Mirrors M1M1 I out I in M3M3 M2M2 V1V1 V2V2 V DD R in R out V out + - + - + - 출력저항 (R out )

61 (7) Wilson Current Mirror (2) Operating Range : Down to V TH  M2M2 I out V SS IinIin M1M1 V TH  M3M3  V DS Mismatch V DS1 = V GS3  V GS2 = V GS3  V DS2  V DS2 Operating Range : Down to V TH  Improved Version Same Performance but V DS1 = V GS3  V GS2  V GS4 = V GS3  V DS2  V GS4 M2M2 I out V SS IinIin M1M1 V TH  M4M4  M3M3  V DS2 59 5. Current Sources & Mirrors

62 (8) Cascode Current Mirror (1) Operating Range : Down to V TH  Output Resistance : R out = (g m4 r o4 )r o2 V DS Mismatch Avoided V DS1 = V GS4  V GS2  V DS2 Operating Range Improved Version :  M2M2 I out V SS IinIin M1M1 V TH  M4M4  M3M3 I out V SS IinIin   V TH  V TH   V DS2 Output Resistance : R out = (g m r o )r o 60 5. Current Sources & Mirrors

63 61 M1M1 M2M2 M3M3 M4M4 M1M1 M2M2 M2M2  M1 : saturation  M2 : saturation (8) Cascode Current Mirror (2) Small signal analysis 5. Current Sources & Mirrors

64 62 M1M1 M2M2 M3M3 M4M4 M5M5 M6M6 M1M1 M2M2 M3M3  M1 : saturation  M2 : saturation  M3 : saturation (8) Cascode Current Mirror (3) 5. Current Sources & Mirrors

65 63 Ma 1 Mb 1 Ma 0 Mb 0 Ma 2 Mb 2 Ma 3 Mb 3 Ma n Mb n V DD (8) Cascode Current Mirror (4) 5. Current Sources & Mirrors