Introduction 2007년 2학기

The Art of Managing Complexity Abstraction Discipline The Three –Y’s Hierarchy Modularity Regularity

Abstraction Hiding details when they aren’t important

Discipline Intentionally restricting your design choices to work more productively at a higher level of abstraction Example: Digital discipline Considering discrete voltages instead of continuous voltages used by analog circuits Digital circuits are simpler to design than analog circuits – can build more sophisticated systems Digital systems replacing analog predecessors: I.e., digital cameras, digital television, cell phones, CDs

The Three -Y’s Hierarchy Modularity Regularity A system divided into modules and submodules Modularity Having well-defined functions and interfaces Regularity Encouraging uniformity, so modules can be easily reused

The Digital Abstraction Most physical variables are continuous, for example Voltage on a wire Frequency of an oscillation Position of a mass Instead of considering all values, the digital abstraction considers only a discrete subset of values

The Analytical Engine Designed by Charles Babbage from 1834 – 1871 Considered to be the first digital computer Built from mechanical gears, where each gear represented a discrete value (0-9) Babbage died before it was finished

Digital Discipline: Binary Typically consider only two discrete values: 1’s and 0’s 1, TRUE, HIGH 0, FALSE, LOW 1 and 0 can be represented by specific voltage levels, rotating gears, fluid levels, etc. Digital circuits usually depend on specific voltage levels to represent 1 and 0 Bit: Binary digit

George Boole, 1815 - 1864 Born to working class parents Taught himself mathematics and joined the faculty of Queen’s College in Ireland. Wrote An Investigation of the Laws of Thought (1854) Introduced binary variables Introduced the three fundamental logic operations: AND, OR, and NOT.

Logic Gates Perform logic functions: inversion (NOT), AND, OR, NAND, NOR, etc. Single-input: NOT gate, buffer Two-input: AND, OR, XOR, NAND, NOR, XNOR Multiple-input

Single-Input Logic Gates

Two-Input Logic Gates

More Two-Input Logic Gates

Multiple-Input Logic Gates

Logic Levels Define discrete voltages to represent 1 and 0 For example, we could define: 0 to be ground or 0 volts 1 to be VDD or 5 volts But what if our gate produces, for example, 4.99 volts? Is that a 0 or a 1? What about 3.2 volts?

Logic Levels Define a range of voltages to represent 1 and 0 Define different ranges for outputs and inputs to allow for noise in the system Noise is anything that degrades the signal For example, a gate (driver) could output a 5 volt signal but, because of losses in the wire and other noise, the signal could arrive at the receiver with a degraded value, for example, 4.5 volts

Logic Levels

Noise Margins NMH = VOH – VIH NML = VIL – VOL

DC Transfer Characteristics Ideal Buffer: Real Buffer: NMH = NML = VDD/2 NMH , NML < VDD/2

DC Transfer Characteristics

The Static Discipline Logic Family VDD VIL VIH VOL VOH TTL 5 (4.75 - 5.25) 0.8 2.0 0.4 2.4 CMOS 5 (4.5 - 6) 1.35 3.15 0.33 3.84 LVTTL 3.3 (3 - 3.6) LVCMOS 0.9 1.8 0.36 2.7

How do We Build Logic Gates? Transistors!

Robert Noyce, 1927 - 1990 Nicknamed “Mayor of Silicon Valley” Cofounded Fairchild Semiconductor in 1957 Cofounded Intel in 1968 Co-invented the integrated circuit

Transistor Basics Transistor is a three-ported voltage-controlled switch Two of the ports are connected depending on the voltage on the third port For example, in the switch below the two terminals (d and s) are connected (ON) only when the third terminal (g) is 1

Transistor Function

CMOS Gates: NOT Gate A P1 N1 Y ON OFF 1

CMOS Gates: NAND Gate A B P1 P2 N1 N2 Y ON OFF 1

Other CMOS Gates Two-input AND gate

Gordon Moore, 1929 - Cofounded Intel in 1968 with Robert Noyce. Moore’s Law: the number of transistors on a computer chip doubles every year (observed in 1965) Since 1975, transistor counts have doubled every two years.

Integrated Circuits The first IC at 1961; 10 Transistors Itanium 2 at 2003; 410M Transistors

Logic transistors per chip Moore’s law The most important trend in the whole IT industry Predicted in 1965 by Intel co-founder Gordon Moore “IC transistor capacity doubles every 18 months” 10,000 1,000 100 10 1 0.1 0.01 0.001 Logic transistors per chip (in millions) 1981 1983 1985 1987 1989 1991 1993 1995 1997 1999 2001 2003 2005 2007 2009

Graphical illustration of Moore’s law Something that doubles frequently grows more quickly than most people realize A 2002’s chip can hold about 15,000 1981’s chips inside itself 1981 1984 1987 1990 1993 1996 1999 2002 10,000 transistors 150,000,000 transistors Leading edge chip in 1981 Leading edge chip in 2002

IC Complexity growth

Productivity-complexity gap While designer productivity has grown at an impressive rate over the past decades, the rate of improvement has not kept pace with chip capacity Means: IC design is getting harder than ever Current generation SOCs have as many as 400M logic transistors With current generation productivity (less than 10K transistors per MM), more than 40K Man-Month is required for design of such an SOC Current 0.13u SOC: 10M$ ~100M$ design cost 10,000 1,000 100 10 1 0.1 0.01 0.001 Logic transistors per chip (in millions) 100,000 1000 Productivity (K) Trans./Staff-Mo. 1981 1983 1985 1987 1989 1991 1993 1995 1997 1999 2001 2003 2005 2007 2009 IC capacity productivity Gap

Evolution of Design

Gate Level (Schematic) Register Transfer Level 설계 계층 레벨 추상적 설계 System Level (컴퓨터, 디스크 장치, 버스 인터페이스 등) Gate Level (Schematic) (NAND, NOR, Flip-flop 등) Chip Level (마이크로프로세서, RAM, ROM, UART 등) Circuit Level (Transistor, Resistor, Capacitor, Inductor 등) Register Transfer Level (레지스터, ALU, 카운터, MUX 등) Layout Level (Poly, Diffusion, Metal, Contact Layer 등) 구체적 설계

A solution for productivity improvement Design in higher (or user friendlier) level of Abstraction For example, use C instead of Assembly language

VHDL Overview What is VHDL ? VHSIC program History of VHDL An industry standard language used to describe hardware from the abstract to the concrete level VHSIC Hardware Description Language VHSIC program Very High Speed Integrated Circuit Funded by the Department of Defense Late 1970s ~ early 1980s To produce the next generation of integrated circuits History of VHDL Very High speed Integrated Circuit(VHSIC) Program Launched in 1980. Proposed in 1981 as an offshoot of the VHSIC program In 1983, a team of Intermetrics, IBM and TI were awarded a contract to develop VHDL. Adopted as the IEEE standard in December 1987 IEEE 1076-1987 Standard VHDL In 1988, adopted as an ANSI standard. In 1993, VHDL was re-standardized to clarify and enhance the language.

VHDL Overview (continued) Why was VHDL proposed ? The tools that were available (before VHDL) to the designers were mostly based at the gate level The gate-level tools were inadequate for large-scale designs Goals of VHDL A language that could describe the complex circuits that the designers were trying to describe, at the Register Transfer Level (RTL). A language that was a standard Applications of VHDL Documentation Simulation Synthesis

Integrated circuits (IC) 설계 변천 과정 How the productivity has grown in the past decades 설계단계 제 1 단계 (60년∼70년대) 제 2 단계 (80년대-90년대 초) 제 3 단계 (90년대 중반 이후) 설계 방법 트랜지스터 레벨의 레이아웃 설계 Gate level이나 Register Transfer level (RTL)의 논리 설계 알고리듬이나 기능 레벨의 고급 설계 설계 도구 Layout 편집기 Schematic 편집기 HDL과 합성기 (Synthesizer, Compiler) 설계 범위 SSI, MSI (103 Gate 이하) LSI, VLSI (103∼105 Gate) VLSI, GSI (105 Gate 이상) 설계 예 기본게이트, 감/가산기 , 멀티플렉서, 카운터 마이크로프로세서, 주변장치 고성능 마이크로프로세서, 실시간 영상처리기

HDL을 이용한 HW설계와 기존 SW programming과의 비교

HDL의 종류 언어 특징 비고 VHDL 높은 기술능력 알고리즘 구현에 많이 사용됨 Verilog HDL 산업체에서 많이 사용. ABEL-HDL VHDL보다 낮은 레벨의 언어 DATA I/O사에서 개발 AHDL Altera사의 HDL Altera사의 제품에만 적용

Benefits of standard HDL Provides a mechanism for digital design and reusable design documentation Provides technology independence Eases communication through standard language Allows for better design management Allows for various design methodologies Describes a wide variety of digital hardware Reduce cycle times for Logic Design Enables hardware modeling from the gate to system level

Design Flow Overview

VHDL의 기본

VHDL Model Components Entity Architecture 하드웨어 외부입출력 인터페이스를 정의 하드웨어 블록의 이름과 입출력 PORT를 선언 Architecture 하드웨어의 내부를 표현 내부회로의 연결, 동작 또는 구조를 표현.

VHDL example entity XOR2_OP is -- Input/Output ports port (A, B : in BIT; Z : out BIT); end XOR2_OP; Interface architecture EXD of XOR2_OP is -- declarations go before begin begin Z <= A xor B; end EXD 내부

Entity Declarations The primary purpose of the entity is to declare the signals in the component’s interface The interface signals are listed in the PORT clause PORT clause declares the interface signals of the object to the outside world Declaration syntax : PORT (signal_name : mode data_type); port (A, B : in BIT; Z : out BIT); example

Entity – Signal Mode The port mode of the interface describes the direction in which data travels with respect to the component In : data comes in this port and can only be read Out : data travels out this port Buffer : data may travel in either direction, but only one signal driver may be on at any one time: Out의 기능과 같으며 외부의 신호를 입력 받을 수 없고, 단지 자신의 신호를 되 읽는 경우에 사용하며 주로 Counter의 경우와 같이 자신의 값을 읽어 증가하거나 감소시킬 때 사용한다 Inout : data may travel in either direction with any number of active drivers allowed ; requires a Bus Resolution Function

Signal Mode out in Architecture inout buffer

Entity – Signal Type 1bit signal: bit, std_logic 2bit이상의 signal: bit_vector, std_logic_vector 2bit -- bit_vector(1 downto 0) std_logic_vector(1 downto 0) 4bit -- bit_vector(0 to 3) std_logic_vector(0 to 3) std_logic, std_logic_vector : IEEE 1164 Standard Signal Type으로 std_logic, std_logic_vector 이 사용될 때는 아래의 문장이 Entity문장 전에 미리 사용 되어야 함. Library ieee; Use ieee.std_logic_1164.all;

downto : 내림차순 표현 to : 오름차순 표현 port( y: buffer std_logic_vector (3 downto 0)); y <= “0011”; -- y(3) = 0, y(2)=0, y(1)=1, y(0)=1 port( y: buffer std_logic_vector (0 to 3)); y <= “0011”; -- y(0) = 0, y(1)=0, y(2)=1, y(3)=1

Architecture Bodies Describe the operation of the component Consist of two parts : Declarative part - includes necessary declarations type declarations, signal declarations, component declarations, subprogram declarations Statement part - includes statements that describe organization and/or functional operation of component concurrent signal assignment statements, process statements, component instantiation statements architecture architecture _이름 is [선언문] begin 동작 표현 end architecture _이름

Entity and Architecture example LIBRARY library_name; USE library_name.package_name.ALL; ENTITY entity_name IS PORT( input_name, input_name : IN STD_LOGIC; input_vector_name : IN STD_LOGIC_VECTOR (high DOWNTO low); bidir_name, bidir_name : INOUT STD_LOGIC; output_name, output_name : OUT STD_LOGIC ); END entity_name; ARCHITECTURE a OF entity_name IS SIGNAL signal_name : STD_LOGIC; BEGIN -- Process Statement -- Concurrent Procedure Call -- Concurrent Signal Assignment -- Conditional Signal Assignment -- Selected Signal Assignment -- Component Instantiation Statement -- Generate Statement END a; Declarative part Statement part

Simple VHDL Code : AND Gate Signal Type으로 std_logic이 사용될 때는 항상 사용. Library ieee; Use ieee.std_logic_1164.all; Entity and_2 is port( a, b : in std_logic; y : out std_logic ); end and_2; Architecture dataflow of and_2 is begin y <= a and b; end dataflow; Entity 문장 : 입력 a,b, 출력 y를 나타냄 Architecture Body : 회로의 설명

VHDL 표현방식

VHDL 표현방식 방법 - 강의순서 데이터 흐름 기술 (Dataflow Descriptions) 부울대수를 이용해서 표현 동작 기술 (Behavioral Descriptions) 알고리즘 적인 방식으로 표현 구조적 기술 (Structural Descriptions) 전체 구조를 단순한 선과 게이트의 연결로 표현 혼합적 기술 (Mixed Descriptions) 위의 3가지방법을 혼합

VHDL 표현방식: Dataflow Description

Dataflow Descriptions 입력과 출력과의 관계를 기술한 부울 대수식을 이용한 설계방식 문장의 순서는 무관하다 병행처리문 (Concurrent Statement)을 주로 사용

Example: Dataflow description: 2 입력 AND Gate Library ieee; Use ieee.std_logic_1164.all; Entity and_2 is port( a, b : in std_logic; y : out std_logic ); end and_2; Architecture dataflow of and_2 is begin y <= a and b; end dataflow; Dataflow방식은 부울대수를 그대로 표현

Statements 병행(Concurrent) Statement 순차(Sequential Statements) Signal Assignment, Simple Signal Assignment, Conditional Signal Assignment, Selected Process Statement 순차(Sequential Statements) If Statement Case Statement For Loop Statement

Concurrent statement - Simple Signal Assignment signal_name <= expression; y <= b; 1) b에 변화가 생길 때마다 b의 값이 y에 출력됨 2) Sensitivity List : b y <= a or b; 1) a 나 b에 변화가 생길 때마다 a or b의 값이 y에 출력됨. 2) Sensitivity List : a,b

Example, Dataflow - 2입력 OR Gate Library ieee; Use ieee.std_logic_1164.all; Entity or_2 is port( a, b : in std_logic; y : out std_logic ); end or_2; Architecture dataflow of or_2 is begin y <= a or b; end dataflow;

Concurrent - Conditional Signal Assignment signal <= expression1 WHEN boolean_expression1 ELSE expression2 WHEN boolean_expression2 ELSE expression3; 1) boolean_expression1= 참(True)이면 signal <= expression1이 실행되며, 2) boolean_expression2= 참(True) 이면 signal <= expression2이 실행되며, 3) 위의 2가지 조건이 모두 성립하지않으면 signal <= expression3이 실행된다.

Concurrent - Selected Signal Assignment WITH expression SELECT signal <= expression1 WHEN constant_value1, expression2 WHEN constant_value2, expression3 WHEN constant_value3; 1) expression = constant_value1 이면 signal <= expression1이 실행되며, 2) expresion1 = constant_value2 이면 signal <= expression2이 실행되며, 3) expresion1 = constant_value3 이면 signal <= expression3이 실행된다.

Concurrent – Process Statement Process문의 내부는 sequential statement 복잡한 알고리즘의 구현 시 편리 (Algorithm은 sequential 한 경우가 대부분) Declaration syntax : [Label:] process [( Sensitivity List)] begin Sequential statements; end process [Label];  Sensitivity List에 적혀있는 신호에 변화생길 때 begin과 end process내의 문장을 실행

객체(Object) 값을 가질 수 있는 변수 (object)는 아래의 3가지 종류 Signal (<= 사용) Variable (:= 사용) Constant (:= 사용) The scope of an object is as follows : Objects declared in a package are available to all VHDL descriptions that use package Objects declared in an entity are available to all architecture associated with that entity Objects declared in an architecture are available to all statements in that architecture Objects declared in a process are available only within that process

객체(Object) - Signals 합성 시에 실제 Wire로 구현 되는 object <= 사용 <= 의 오른쪽에서 왼쪽으로 대입 Process 문 내에서 <= 로 대입되었다면 즉시 수행되는 것이 아니라 end process를 만나야만 수행 됨 Signal의 초기화에는 := 를 사용 Port로 선언하여도 signal임 (port signal) Declaration syntax : 사용 예 signal a, b : std_logic;  선언 a<= ‘1’; b<=‘0’;  Signal a,b에 값 ‘1’, ‘0’을 대입. SIGNAL signal_name : type_name [ :=value];

Example: Dataflow - Andor_2 library ieee; use ieee.std_logic_1164.all; entity andor_2 is port( a, b, c : in std_logic; y : out std_logic); end andor_2; architecture a of andor_2 is signal t : std_logic; begin t<=a and b; y<=t or c; end a;

객체(Object) - Variable Provide convenient mechanism for local storage Scope is within process in which they are declared All variable assignments take place immediately Declaration syntax : 사용 예 variable a, b : std_logic;  선언 a := ‘1’; b :=‘0’;  Variable a,b에 값 ‘1’,’0’을 대입 VARIABLE variable_name : type_name [ :=value];

객체(Object) - Constants Name assigned to a specific value of a type Allow for easy update and readability Declaration syntax : 사용 예 constant bits3_0 : std_logic_vector(2 downto 0) := "000";  선언 y<= bits3_0;  Signal y에 값 “000”을 대입 CONSTANT constant_name : type_name [ :=value];

Dataflow – 4 bits OR gate library ieee; use ieee.std_logic_1164.all; entity or_4bits is port( a, b : in std_logic_vector(3 downto 0); y : out std_logic_vector(3 downto 0) ); end or_4bits; architecture xxx of or_4bits is begin y <= a or b; end xxx; Bus의사용

Dataflow - Half Adder library ieee; Use ieee.std_logic_1164.all; Entity half_add is port( a,b : in std_logic; sum, c_out : out std_logic ); end half_add; Architecture dataflow of half_add is begin sum <= A xor B; c_out <= A and B; end dataflow; 문장의 순서는 무관

Operators Defined precedence levels in decreasing order : Miscellaneous operators -- ** (exponential), abs, not Multiplication operators -- *, /, mod (modulus), rem (remainder) Sign operator -- +,- Addition operators – sll (logical shift left), srl, sla (arithmetic shift left), sra, rol (logical rotate left), ror Relational operators -- =, /=, <, <=, >, >= Logical operators -- AND, OR, NAND, NOR, XOR, XNOR

Attribute Attributes provide information about certain items in VHDL: X’EVENT -- TRUE when there is an event on signal X X’LAST_VALUE -- returns the previous value of signal X Y’HIGH -- returns the highest value in the range of Y X’STABLE(t) -- TRUE when no event has occurred on signal X in the past ‘t’ time

Structural Description VHDL 표현방식: Structural Description

Structural Descriptions 구성 요소 및 연결 자체를 표현 Graphic Editor를 이용한 고전적인 설계방식과 동일. Component( ) 문을 이용하여 선언 Port map( ) 문을 이용하여 핀들을 서로 연결. 위치결합(positional association) Port문 내의 Signal의 위치순서대로 나열 이름결합(named association) Port문 내의 Signal의 위치순서와는 상관없이 ( port문 내의 형식이름=> 실제 이름)의 방식으로 결합.

Structure - Andor_2 library ieee; use ieee.std_logic_1164.all; and_2.vhd, or_2.vhd는 미리 작성된 상태임. library ieee; use ieee.std_logic_1164.all; entity andor_2 is port( a, b, c : in std_logic; y : out std_logic); end andor_2; architecture a of andor_2 is component and_2 port( and_in1, and_in2 : in std_logic; and_out : out std_logic ); end component; component or_2 port( or_in1, or_in2 : in std_logic; or_out : out std_logic ); signal t : std_logic; begin U1 : and_2 port map ( a, b, t ); U2 : or_2 port map (or_in1=> t, or_in2=>c , or_out=>y); end a; And_2선언 and_in1 and_in2 and_out A B T T or_in1 or_out Y Or_2선언 C or_in2 positional association named association

Behavioral Description VHDL 표현방식: Behavioral Description

Behavioral Descriptions 기능적 또는 알고리즘적 표현 고급언어를 사용한 프로그램 작성방법과 유사 Process 사용이 가장 중요한 부분 Process내부에서 sequential statement를 사용

Behavioral description - Conditional Signal Assignment library ieee; use ieee.std_logic_1164.all; entity mux21_when is port( a,b : in std_logic; s : in std_logic; y : out std_logic); end mux21_when; architecture a of mux21_when is begin y <= a when (s='0') else b; end a; 회로보다는 동작에 관심. 마지막 조건은 else 로 처리해야 함

Behavioral - Selected Signal Assignment, library ieee; use ieee.std_logic_1164.all; entity mux21_with is port( a, b: in std_logic; s : in std_logic; y : out std_logic); end mux21_with; architecture a of mux21_with is BEGIN WITH s SELECT y <= a WHEN ‘0’, b WHEN others; END a; 마지막 조건은 others 로 처리해야 함

 Sensitivity List에 적혀있는 Process - Recap Process문의 내부는 sequential statement 복잡한 알고리즘의 구현 시 편리 (Algorithm은 sequential 한 경우가 대부분) Declaration syntax : [Label:] process [( Sensitivity List)] begin Sequential statements; end process [Label];  Sensitivity List에 적혀있는 신호에 변화생길 때 begin과 end process내의 문장을 실행 Optional

Sequential Statement: IF IF expression1 THEN statement1-1; statement1-2; ELSIF expression2 THEN statement2-1; statement2-2; ELSE statement3-1; statement3-2; END IF; 1) expression1 = 참(True)이면 statement1-1, state1-2가 실행, 2) expression2 = 참(True) 이면 statement2-1, state2-2가 실행, 3) 위의 2가지 조건 모두 성립하지않으면 statement3-1, state3-2가 실행,

Behavioral – Sequential Statement (IF) library ieee; use ieee.std_logic_1164.all; entity mux21_if_proc is port( a,b : in std_logic; s : in std_logic; y : out std_logic); end mux21_if_proc; architecture proc of mux21_if_proc is begin process(a,b,s) if( s='0') then y<=a; else y<=b; end if; end process; end proc; a, b,s 에 변화생길 때 실행 마지막 조건은 else로 처리해야 함.

Sequential Statement: Case CASE expression IS WHEN constant_value1 => statement1-1; statement1-2; WHEN constant_value2 => statement2-1; statement2-2; WHEN OTHERS => statement3-1; statement3-2; END CASE; 1) expression1 = constant_value1 이면 statement1-1, state1-2가 실행, 2) expression1 = constant_value1 이면 statement2-1, state2-2가 실행, 3) 위의 2가지 조건 모두 성립하지않으면 statement3-1, state3-2가 실행,

Behavioral – Sequential Statement (case) library ieee; use ieee.std_logic_1164.all; entity mux21_case_proc is port( a,b : in std_logic; s : in std_logic; y : out std_logic); end mux21_case_proc; architecture proc of mux21_case_proc is begin process(a,b,s) case s is when '0' => y<= a; when others => y<= b; end case; end process; end proc; 마지막 조건은 others로 처리해야 함.

Sequential – For Statement loop_label: FOR index_variable IN range LOOP statement1; statement2; END LOOP loop_label; index_variable 의 값을 변해가면서 statement1, statement2를 반복적으로 실행. 아래의 (a), (b)는 모두 같은 표현임. Range는 downto, to의 2가지형태임. loop_Start: FOR i IN 0 to 3 LOOP y(i) <= a(i) and b(i); END LOOP loop_Start; (a) y(0) <= a(0) and b(0); y(1) <= a(1) and b(1); y(2) <= a(2) and b(2); y(3) <= a(3) and b(3); (b)

Behavioral – Signal vs. Variable library ieee; use ieee.std_logic_1164.all; entity andor_2 is port( a, b, c : in std_logic; y : out std_logic); end andor_2; architecture a of andor_2 is Begin process(a,b,c) variable t : std_logic; begin t :=a and b; y<=t or c; end process; end a; library ieee; use ieee.std_logic_1164.all; entity andor_2 is port( a, b, c : in std_logic; y : out std_logic); end andor_2; architecture a of andor_2 is signal t : std_logic; Begin process(a,b,c,t) begin t<=a and b; y<=t or c; end process; end a; 선언되는 위치차이 Sensitivity List차이 2 1 1 Signal t는 Process문이 끝나는 순간에 일괄적으로 값이 할당. 2 3 Variable은 대입 즉시 값 할당.

Behavioral – Signal vs. Variable library ieee; use ieee.std_logic_1164.all; entity andor_2 is port( a: in std_logic; y : out std_logic); end andor_2; architecture a of andor_2 is Begin process(a) variable t : std_logic; begin t :=a; y<=t; end process; end a; library ieee; use ieee.std_logic_1164.all; entity andor_2 is port( a: in std_logic; y : out std_logic); end andor_2; architecture a of andor_2 is signal t : std_logic; Begin process(a,t) begin t<=a; y<=t; end process; end a;

참고문헌 PERRY, VHDL 4/E : PROGRAMMING BY EXAMPLE . FLOYD, DIGITAL FUNDAMENTALS WITH VHDL . ARMSTRONG,GRAY, VHDL DESIGN REPRESENTATION & SYNTHESIS. SKHILL, VHDL FOR PROGRAMMABLE LOGIC . PELLERIN, VHDL MADE EASY. LEE, VHDL CODING & LOGIC SYNTHESIS WITH SYNOPSYS.