VHDL 프로그램은 비동기 Reset을 갖는 D 플립플롭을 구현한 것이다 VHDL 프로그램은 비동기 Reset을 갖는 D 플립플롭을 구현한 것이다. 출력 q의 파형을 구하는 Simulation을 수행하라. 과제 LIBRARY ieee; --------------------- USE ieee.std_logic_1164.ALL; -- D FF with Reset ----------------------- ENTITY d_ff IS PORT(cp, n_reset, d : IN std_logic; q : OUT std_logic); END d_ff ; ARCHITECTURE arc OF d_ff IS BEGIN PROCESS (cp, n_reset) IF (n_reset = '0') THEN q<='0'; ELSE IF (cp'EVENT AND cp= '1') THEN q<=d; END IF; END PROCESS; END arc;

그림과 같이 입력하여 출력 q의 파형을 구하는 Simulation을 수행하라.

VHDL 프로그램은 비동기 Set와 Reset을 갖는 D 플립플롭을 구현한 것이다 VHDL 프로그램은 비동기 Set와 Reset을 갖는 D 플립플롭을 구현한 것이다. 출력 q의 파형을 구하는 Simulation을 수행하라. LIBRARY ieee; ------------------------------- USE ieee.std_logic_1164.ALL; -- D FF with Reset and Set-- ------------------------------- ENTITY d_ff_sr IS PORT(cp, n_reset, n_set, d : IN std_logic; q : OUT std_logic); END d_ff_sr ; ARCHITECTURE arc OF d_ff_sr IS BEGIN PROCESS (cp, n_reset, n_set) IF (n_reset = '0'AND n_set='1') THEN q<='0'; ELSIF (n_reset = '1'AND n_set='0') THEN q<='1'; ELSIF (cp'EVENT AND cp= '1') THEN q<=d; END IF; END PROCESS; END arc; 과제

그림과 같이 입력하여 출력 q의 파형을 구하는 Simulation을 수행하라.

J-K flip-flop of VHDL listing 실습 J-K flip-flop of VHDL listing LIBRARY ieee; ----------------------- USE ieee.std_logic_1164.ALL; -- J-K FF ---------------------- ENTITY jk_ff IS PORT(pr, clr, clk, j, k : IN std_logic; q : BUFFER std_logic); END jk_ff; ARCHITECTURE arc OF jk_ff IS SIGNAL jk : std_logic_vector (1 DOWNTO 0); BEGIN jk<=j&k; PROCESS (pr, clr, clk, j, k) if(pr='0' and clr='1') then q <= '1'; elsif(pr='1' and clr='0') then q <= '0'; elsif (clk'EVENT AND clk = '0') THEN --Neg edge trigger CASE jk IS WHEN "00" => q <= q; --Hold WHEN "01" => q <= '0'; --Reset WHEN "10" => q <= '1'; --Set WHEN "11" => q <= NOT q; --Toggle WHEN OTHERS => q <= q; END CASE; END IF; END PROCESS; END arc;

그림과 같이 입력하여 출력 q의 파형을 구하는 Simulation을 수행하라.

Clear(RD)가 있는 16진 up카운터 설계 과제 Clear(RD)가 있는 16진 up카운터 설계 LIBRARY ieee; ----------------------------- USE ieee.std_logic_1164.ALL; -- Mod-16 Up-Counter -- ----------------------------- ENTITY mod16up IS PORT(n_cp, n_rd : IN std_logic; q : BUFFER integer RANGE 0 TO 15); END mod16up; ARCHITECTURE arc OF mod16up IS BEGIN PROCESS (n_cp, n_rd) IF (n_rd='0') THEN q <= 0; ELSIF (n_cp'EVENT AND n_cp='0') THEN q <=q+1; END IF; END PROCESS; END arc;

그림과 같이 입력하여 출력 q의 파형을 구하는 Simulation을 수행하라.

10진 up카운터 설계 과제 LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Mod-10 Up-Counter ENTITY mod_10 IS PORT(n_cp, n_rd IN std_logic; q : BUFFER integer RANGE 0 TO 15); END mod_10; ARCHITECTURE arc OF mod_10 IS BEGIN PROCESS (n_cp, n_rd) IF (n_rd='0' OR q=10) THEN q <= 0; ELSIF (n_cp'EVENT AND n_cp='0') THEN q <=q+1; END IF; END PROCESS; END arc;

그림과 같이 입력하여 출력 q의 파형을 구하는 Simulation을 수행하라.

0부터 7까지 세는 카운터 과제 01 ------ 설계 해 1: VARIABLE 사용 -------- 0부터 7까지 세는 카운터 과제 01 ------ 설계 해 1: VARIABLE 사용 -------- 02 ENTITY counter IS 03 PORT ( clk, rst: IN BIT; 04 count: OUT INTEGER RANGE 0 TO 7); 05 END counter; 06 -------------------------------------------- 07 ARCHITECTURE counter OF counter IS 08 BEGIN 09 PROCESS (clk, rst) 10 VARIABLE temp: INTEGER RANGE 0 TO 7; 11 BEGIN 12 IF (rst='1') THEN 13 temp:=0; 14 ELSIF (clk'EVENT AND clk='1') THEN 15 temp := temp+1; 16 END IF; 17 count <= temp; 18 END PROCESS; 19 END counter; 20 -------------------------------------------- 01 ------ 설계 해 2: SIGNAL만을 사용 ------- 02 ENTITY counter IS 03 PORT ( clk, rst: IN BIT; 04 count: BUFFER INTEGER RANGE 0 TO 7); 05 END counter; 06 -------------------------------------------- 07 ARCHITECTURE counter OF counter IS 08 BEGIN 09 PROCESS (clk, rst) 10 BEGIN 11 IF (rst='1') THEN 12 count <= 0; 13 ELSIF (clk'EVENT AND clk='1') THEN 14 count <= count + 1; 15 END IF; 16 END PROCESS; 17 END counter; 18 --------------------------------------------

그림과 같이 입력하여 출력 q의 파형을 구하는 Simulation을 수행하라.

비동기 Set와 Reset을 갖는 4-bit up-counter 과제 비동기 Set와 Reset을 갖는 4-bit up-counter LIBRARY ieee; --------------------------- USE ieee.std_logic_1164.ALL; -- 4-bit Up-Counter with -- -- Async Reset and Load -- ENTITY counter_a IS ---------------------------- PORT(cp, n_rd, n_pl : IN std_logic; pl_data : IN integer RANGE 0 TO 15; q : BUFFER integer RANGE 0 TO 15); END counter_a; ARCHITECTURE arc OF counter_a IS BEGIN PROCESS (cp, n_rd, n_pl) IF (n_rd='0' AND n_pl='1') THEN q<= 0; ELSIF (n_rd='1' AND n_pl='0') THEN q<=pl_data; ELSIF (cp'EVENT AND cp='1' ) THEN q<=q+1; END IF; END PROCESS; END arc;

그림과 같이 입력하여 출력 q의 파형을 구하는 Simulation을 수행하라.

클럭 인에이블, 병렬로드, 비동기 Set와 Reset을 갖는 4-bit up/down-counter 과제 클럭 인에이블, 병렬로드, 비동기 Set와 Reset을 갖는 4-bit up/down-counter LIBRARY ieee; ---4-bit Up/Down-Counter -- USE ieee.std_logic_1164.ALL; -- with Async Reset and Load -- -- and clock enable -- ENTITY counter_b IS PORT(cp, n_rd, n_pl, n_ce, u_d : IN std_logic; pl_data : IN integer RANGE 0 TO 15; q : BUFFER integer RANGE 0 TO 15); END counter_b; ARCHITECTURE arc OF counter_b IS BEGIN PROCESS (cp, n_rd, n_pl) IF (n_rd='0' AND n_pl='1') THEN q<= 0; ELSIF (n_rd='1' AND n_pl='0') THEN q<=pl_data; ELSIF (cp'EVENT AND cp='1' ) THEN IF (n_ce='0') THEN IF (u_d='0') THEN q<=q+1; ELSE q<=q-1; END IF; END PROCESS; END arc;

그림과 같이 입력하여 출력 q의 파형을 구하는 Simulation을 수행하라.

Count(6 downto 0) & count(7) 과제 8비트 ring counter Count(7) Count(6) Count(5) Count(4) Count(3) Count(2) Count(1) Count(0) Count(6 downto 0) & count(7)

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity ring_counter is port(clk, reset : in std_logic; count : buffer std_logic_vector(7 downto 0)); end ring_counter; architecture sample of ring_counter is begin process(clk, reset) if(reset = '1') then count <="00000001"; elsif (clk'event and clk = '1') then count <=count(6 downto 0) & count(7); end if; end process; end sample;

그림과 같이 입력하여 출력 q의 파형을 구하는 Simulation을 수행하라.

과제 비동기 카운터 설계

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity async_counter is port (clk, reset : in std_logic; count_out : buffer std_logic_vector(7 downto 0)); end async_counter ; architecture sample of async_counter is begin process(clk, reset) if (reset = '1') then count_out <= "00000000"; elsif (clk'event and clk = '1')then count_out <= count_out + 1; end if; end process; end sample;

비동기 카운터 설계

과제 동기 카운터 설계

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity sync_counter is port (clk, reset : in std_logic; count_out : buffer std_logic_vector(7 downto 0)); end sync_counter ; architecture sample of sync_counter is begin process(clk, reset) if clk'event and clk = '1' then if reset ='1' then count_out <= "00000000"; else count_out <= count_out + 1; end if; end process; end sample;

동기 카운터 설계

Mod-12 UP 카운터 설계

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity count12 is port (clk, rst : in std_logic; c_out : buffer std_logic_vector(11 downto 0)); end count12; architecture sample of count12 is begin process(clk, rst) if (rst = '1') then c_out <= (others => '0'); elsif (clk'event and clk = '1')then c_out <= c_out + 1; end if; end process; end sample;

과제 enable과 load입력이 있는 8비트 UP 카운터 설계

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity controlup is port (clk, reset , enable, load : in std_logic; in_data : in std_logic_vector(7 downto 0); count_out : buffer std_logic_vector(7 downto 0)); end controlup ; architecture sample of controlup is signal clken : std_logic; begin clken <= clk and enable; process(clken, reset, load) if reset = '1' then count_out <= "00000000"; elsif (clken'event and clken ='1')then if load = '1' then count_out <= in_data; else count_out <= count_out + '1'; end if; end process; end sample;

enable과 load입력이 있는 8비트 UP 카운터 설계

과제 UPDOWN 카운터 설계

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity updown_coun is port(clk, updn, rst : in std_logic; c_out : buffer std_logic_Vector(11 downto 0)); end updown_coun; architecture sample of updown_coun is begin process(clk, rst) if(rst='1') then c_out <= (others => '0'); elsif(clk'event and clk = '1') then if (updn = '1')then c_out <= c_out + 1; else c_out <= c_out - 1; end if; end process; end sample;

과제 8비트 UP/down 카운터 설계

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity updowncounter is port (clk, reset , up_down, enable, load : in std_logic; in_data : in std_logic_vector(7 downto 0); count_out : buffer std_logic_vector(7 downto 0)); end updowncounter ; architecture sample of updowncounter is signal clken : std_logic; begin clken <= clk and enable; process(clken, reset, load) if reset = '1' then count_out <= "00000000"; elsif (clken'event and clken ='1')then if load = '1' then count_out <= in_data; elsif up_down ='1' then count_out <= count_out + 1; else count_out <= count_out -1; end if; end process; end sample;

8비트 UP/down 카운터 설계

과제 주파수 분배기 클록 주파수를 6으로 나누는 회로 구현 [그림] 주파수 분배기

01 ----------------------------------------------------- 02 LIBRARY ieee; 03 USE ieee.std_logic_1164.all; 04 ----------------------------------------------------- 05 ENTITY freq_divider IS 06 PORT ( clk : IN STD_LOGIC; 07 out1 : BUFFER STD_LOGIC); 08 END freq_divider; 09 ----------------------------------------------------- 10 ARCHITECTURE example OF freq_divider IS 11 SIGNAL count1 : INTEGER RANGE 0 TO 7; 12 BEGIN PROCESS (clk) 15 BEGIN 16 IF (clk'EVENT AND clk='1') THEN count1 <= count1 + 1; 19 IF (count1 = ? ) THEN 20 out1 <= NOT out1; 21 count1 <= 0; END IF; 27 END IF; 28 END PROCESS; 29 END example; 30 ----------------------------------------------------- 01 --------------------------------------------------------- 02 LIBRARY ieee; 03 USE ieee.std_logic_1164.all; 04 --------------------------------------------------------- 05 ENTITY freq_divider IS 06 PORT ( clk : IN STD_LOGIC; 07 out2 : BUFFER STD_LOGIC); 08 END freq_divider; 09 --------------------------------------------------------- 10 ARCHITECTURE example OF freq_divider IS 12 BEGIN 13 PROCESS (clk) 14 VARIABLE count2 : INTEGER RANGE 0 TO 7; 15 BEGIN IF (clk'EVENT AND clk='1') THEN count2 := count2 + 1; 23 IF (count2 = ? ) THEN 24 out2 <= NOT out2; 25 count2 := 0; 26 END IF; 27 END IF; 28 END PROCESS; 29 END example; 30 ---------------------------------------------------------

주파수 분배기 설계

과제 5분주 클럭발생기 설계

elsif (clk'event and clk ='0') then present_state <= next_state; else next_state <= "00001"; end if; end process; Process(clk, reset) begin if reset='1' then present_state <= "00000"; elsif (clk'event and clk ='0') then present_state <= next_state; End process; Out_clk <=present_state; end sample; library ieee; use ieee.std_logic_1164.all; entity clk5DIV is port (clk, reset : in std_logic; out_clk : out std_logic_vector(4 downto 0)); end clk5div ; architecture sample of clk5div is signal present_state, next_state : std_logic_vector( 4 downto 0); begin process(present_state) if present_state="00000" then next_state <= "00001"; elsif present_state="00001" then next_state <= "00010"; elsif present_state="00010" then next_state <= "00100"; elsif present_state="00100" then next_state <= "01000"; elsif present_state="01000" then next_state <= "10000"; elsif present_state="10000" then

5분주 클럭발생기 설계

과제 클럭 분주회로 설계

variable cnt25 : integer range 0 to 7; variable clk25_out : std_logic; outclk200 <=clk200_out; end process; clk25 : Process(clken200) variable cnt25 : integer range 0 to 7; variable clk25_out : std_logic; begin if clken200'event and clken200='0' then if cnt25 < 7 then cnt25 :=cnt25 + 1; elsif cnt25 = 7 then cnt25 :=0; clk25_out :=not clk25_out; end if; outclk25 <=clk25_out; end sample; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity multiclk_div is port (inclk800 : in std_logic; outclk200, outclk25 : out std_logic); end multiclk_div; architecture sample of multiclk_div is signal clken200 : std_logic; begin clk200 : process(inclk800) variable cnt200 : integer range 0 to 3; variable clk200_out : std_logic; if inclk800'event and inclk800='0' then if cnt200 < 3 then cnt200 :=cnt200 + 1; clken200 <='0'; elsif cnt200 = 3 then cnt200 :=0; clk200_out := not clk200_out; clken200 <='1'; end if;

클럭분주회로 설계

키입력에 의한 카운터 설계

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity count1_key is port(key, clk, rst : in std_logic; c_out : buffer std_logic_vector(3 downto 0)); end count1_key; architecture sample of count1_key is signal cen : std_logic; component keyinh port( data, clk : in std_logic; y_out : buffer std_logic ); end component; begin keyevent : keyinh port map(data=>key, clk=>clk,y_out=>cen); keycount : process(clk,rst) if(rst='1')then c_out <= (others => '0'); elsif (clk'event and clk = '1') then if (cen = '1') then c_out <= c_out + 1; end if; end process; end sample;

library ieee; use ieee.std_logic_1164.all; entity keyinh is port(data, clk : in std_logic; y_out : buffer std_logic); end keyinh; architecture sample of keyinh is signal data1 : std_logic; begin process(clk) if(clk'event and clk = '1') then data1 <= data; if (data1='0') and (data = '1') then y_out <= '1'; else y_out <= '0'; end if; end process; end sample;

과제 4단 시프트 레지스터 #2의 VHDL 코드 : 설계 해 1 01 --- 설계 해 1 : 내부 SIGNAL 사용--------------------------- 02 LIBRARY ieee; 03 USE ieee.std_logic_1164.all; 04 ---------------------------------------------------------------- 05 ENTITY shiftreg IS 06 PORT ( d, clk, rst: IN STD_LOGIC; 07 q: OUT STD_LOGIC); 08 END shiftreg; 09 ---------------------------------------------------------------- 10 ARCHITECTURE behavior OF shiftreg IS 11 SIGNAL internal: STD_LOGIC_VECTOR (3 DOWNTO 0); 12 BEGIN 13 PROCESS (clk, rst) 14 BEGIN 15 IF (rst='1') THEN 16 internal <= (OTHERS => '0'); 17 ELSIF (clk'EVENT AND clk='1') THEN 18 internal <= d & internal(3 DOWNTO 1); 19 END IF; 20 END PROCESS; 21 q <= internal(0); 22 END behavior;

4단 시프트 레지스터 #2의 VHDL 코드 : 설계 해 2 과제 4단 시프트 레지스터 #2의 VHDL 코드 : 설계 해 2 01 --- 설계 해 2 : 내부 VARIABLE 사용------------------------------- 02 LIBRARY ieee; 03 USE ieee.std_logic_1164.all; 04 ---------------------------------------------------------------------- 05 ENTITY shiftreg IS 06 PORT (d, clk, rst: IN STD_LOGIC; 07 q: OUT STD_LOGIC); 08 END shiftreg; 09 ---------------------------------------------------------------------- 10 ARCHITECTURE behavior OF shiftreg IS 11 BEGIN 12 PROCESS (clk, rst) 13 VARIABLE internal: STD_LOGIC_VECTOR (3 DOWNTO 0); 14 BEGIN 15 IF (rst='1') THEN 16 internal := (OTHERS => '0'); 17 ELSIF (clk'EVENT AND clk='1') THEN 18 internal := d & internal(3 DOWNTO 1); 19 END IF; 20 q <= internal(0); 21 END PROCESS; 22 END behavior;

그림과 같이 입력하여 출력 q의 파형을 구하는 Simulation을 수행하라.

4비트 이동레지스터 -- srg4behv.vhd -- Behavioral description of a 4-bit serial shift register LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY srg4behv IS PORT( serial_in, clk : IN STD_LOGIC; q : BUFFER STD_LOGIC_VECTOR(3 downto 0)); END srg4behv; ARCHITECTURE right_shift of srg4behv IS BEGIN PROCESS (clk) IF (clk'EVENT and clk = '1') THEN q(3 downto 0) <= serial_in & q(3 downto 1); END IF; END PROCESS; END right_shift;

비동기 클리어를 가진 4비트 양방향 이동레지스터 LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY srg4bidi IS PORT( clk, clear : IN STD_LOGIC; rsi, lsi : IN STD_LOGIC; direction : IN STD_LOGIC; q : BUFFER STD_LOGIC_VECTOR(3 downto 0)); END srg4bidi; ARCHITECTURE bidirectional_shift of srg4bidi IS BEGIN PROCESS (clk, clear) IF clear = '0' THEN q <= (others => '0'); -- asynchronous clear ELSIF (clk'EVENT and clk = '1') THEN CASE direction IS WHEN '0' => q <= q(2 downto 0) & lsi; -- left shift WHEN '1' => q <= rsi & q(3 downto 1); -- right shift WHEN others => NULL; END CASE; END IF; END PROCESS; END bidirectional_shift;

과제 left/right시프트가 가능한 4비트 시프트 레지스터

left/right시프트가 가능한 4비트 시프트 레지스터 library ieee; use ieee.std_logic_1164.all; entity bidir_shiftreg4 is port(clk, reset : in std_logic; in_data : in std_logic; le_ri : in std_logic; in_reg : in std_logic_vector(3 downto 0); out_reg : buffer std_logic_vector(3 downto 0)); end bidir_shiftreg 4; architecture test of bidir_shiftreg4 is begin process(clk, reset, le_ri) if reset ='1' then out_reg <= in_reg; elsif(clk'event and clk='1') then if le_ri='0' then out_reg <=out_reg(2 downto 0) & in_data; else out_reg <=in_data & out_reg(3 downto 1); end if; end process; end test;

left/right시프트가 가능한 4비트 시프트 레지스터