디지털 시스템 설계(3)
Design Flow Design Specification Schematic Design VHDL Design Entry Verilog HDL Design Entry Delta Delay를 적용하여 입력된 Test Waveform(Test Bench Timing file)을 이용) Design Modification Function Verification Timing Verification Device Delay를 적용하여 입력된 Test Waveform(Test Bench Timing file)을 이용) Device Programming In-System Verification System Production
Design Software Main menu file New Project Wizard(5단계로 이루어짐) 1.(page 1 of 5) Entity 입력시 Top-Level의 Entity 이름과 같게… 2.(page 3 of 5) 디바이스 선택(EP2C35F672) Project 선언 Main menu file New Block Diagram/Schematic file VHDL Verilog HDL Design Entry Compile Main menu Processing Start Compilation Assignment (Device) Main menu Assignments Device : Device 선택(EP2C35F672) Assignment (Pin) Main menu Assignments Assignment Editor : Pin 선택 Function Simulation Main menu file New Vector Waveform File Main menu Processing Start Simulation
실습(ex1-1) 입 력 출 력 A B C Y 1
실습(ex1-2) 입 력 출 력 A B Y 1
실습(ex1-3) 입 력 출 력 A C Y 1
실습(ex1-4) 입 력 출 력 A1 A2 B1 B0 C1 S1 S0 C0 1